1. Field of the Invention
The present invention relates to a microcomputer, in particular, a microcomputer having a power saving function.
2. Description of Related Art
A standby mode (power saving mode) is adopted in microcomputers. In the standby mode, various measures such as a reduction in the clock frequency of the CPU, a reduction in the power supply voltage, a suspension of the clock supply to the CPU, and/or a suspension of the power supply to the CPU are performed.
Japanese Unexamined Patent Application Publication No. 2008-59300 discloses a microcomputer to achieve the reduction in the power consumption. FIG. 9 shows a configuration of this microcomputer. This microcomputer 300 has, in addition to the normal operation mode, a deep standby mode where an internal power supply 1 is cut off and the clock of a CPU 310 is suspended.
Under instructions from a power control unit 340, a power supply circuit 330 generates two types of internal power supplies by lowering the voltage of the electric power supplied from the outside of the LSI, and supplies the generated internal power supplies into the LSI. The internal power supply 1 is cut off during the deep standby mode. An internal power supply 2 is supplied even in the deep standby mode. IO buffers 320a and 320b output internal signals of the LSI to the outside of the LSI, and supply input signals supplied from the outside of the LSI into the LSI. The IO buffers 320a and 320b are divided into a plurality of groups, and their terminal states during a deep standby mode and immediately after a recovery from the deep standby mode can be controlled on a group-by-group basis. As for the terminal states in the IO buffers 320a and 320b during the deep standby mode, when it is “terminal is to be held”, they hold the states immediately before the deep standby mode (inputs/outputs, output values), whereas when it is “terminal is not to be held”, they become high-impedance (HiZ) states. As for the terminal states in the IO buffers 320a and 320b at the recovery from the deep standby mode, when it is “terminal is to be held”, they hold the terminal states until a certain operation is performed, whereas when it is “terminal is not to be held”, they change to the reset states. Since the internal power supply 1 is cut off during the deep standby mode, the leak current can be reduced.
Data latches (LATs) 321 are provided within the IO buffer 320. FIG. 10 shows a configuration diagram of the IO buffer 320. The data latches 321 hold an IO output state until the recovery from the deep standby mode. In this way, when the LSI is recovered from the deep standby mode, it is possible to carry out a booting process and a series of subsequent processes by using information held by the data latches 321. Voltage-boosting circuits 322 and voltage-lowering circuits 323 are circuits that are used to convert the voltage level of signals.